1. Field of the Invention
The invention relates to a method for clock-data recovery and an associated device.
2. Discussion of the Background
In digital transmission technology, many binary data streams, especially serial data streams are transmitted at a fast bit rate without an accompanying clock-data signal. The goal of clock-data recovery (CDR) is to determine the frequency and phase of the underlying transmission clock data from the received data stream.
In a conventional receiver, the recovered clock signal is used for decoding the transmitted bit sequence by sampling the received signal pulses exactly in the center in order to maximize the signal-noise ratio. In signal analysis, the recovered clock signal is used to evaluate the signal quality, typically with reference to so-called eye diagrams and mathematical tools for jitter analysis.
The transmitted clock pulse is often determined by means of a PLL (Phase-Locked Loop), a phase-locked control loop. For the analysis of signal quality, various standards specify a standardized receiver in the form of PLL properties. In this context, the recovered clock signal determines the ideal bit starting point according to definition. The evaluation of deviations between the zero passes in the received data stream and in the clock signal forms the basis of the data analysis.
For signal analysis or jitter analysis, the transmitted clock pulse is recovered, in principle, in two different ways:                The PLL is realized with hardware components. The user feeds the time-continuous data stream into the PLL and receives in return a time-continuous clock signal and the data stream delayed by the processing latency. The data stream and clock signal are synchronized with one another. The method operates online in real time; the data stream is constantly observed.        The PLL is simulated in software with a rule for computation. A test device takes up one portion of the data stream and applies the clock-data recovery algorithm to it. The clock signal for the recorded data portion is recovered from this. This method generally operates offline, because the processing time of the algorithm is longer than the time duration of the recorded data portion.        
Hardware PLLs known in the prior art can be subdivided into three categories: linear PLLs, digital PLLs and all-digital PLLs. The three types of PLL process and generate analog, time-continuous signals, wherein the digital and all-digital PLLs are adapted to the processing of binary serial data streams.
The rule for computation, which simulates the method of functioning of a hardware PLL, is generally referred to as a software PLL. One approach is to describe the method of operation of the analog components mathematically and to process a highly-sampled version of the received data stream with this. A second approach is based on the observation that only the zero passes in the data stream contain the relevant information for the clock-data recovery. In this case, the position of the zero passes is initially determined by interpolation of the stored data portion, and the zero passes of the clock signal are then calculated from this.
FIG. 1 shows the simplified structure of a software PLL according to the latter approach of the prior art. The input signal x0(k) is a list with the position in time of the zero passes in the data stream, also referred to below as data edges. The calculated clock edges are described by y(k). The PLL generates only one clock edge per bit period. If the underlying, time-continuous clock signal is imagined as a sinusoidal oscillation, then y(k) designates the timing points with phase equal to 0.
The x0(k) are sorted chronologically and processed sequentially. Initially, the time difference e(k) between data edges and clock edges is formed in the phase detector. Since no signal throughput takes place when the transmitter transmits two or more identical bits in succession, the number of data-edges is generally smaller than the number of bits transmitted. If the time-difference value is greater than one half bit period T0, a missing edge can be assumed, and, by way of example, e(k)=0 is set; otherwise, the phase detector passes on the time difference e(k) without change. The term e(k) is filtered with the loop filter F(q−1)·F(q−1) describes a differential equation as a function of the delay operator q−1, for which the following applies by way of example: 2·q−1·e(k)=2·e(k−1). The resulting d(k) together with a constant T0, which indicates the nominal bit period of the data stream, provides an estimate of the momentary bit period of the data stream. The accumulator A(q−1) determines the position of the next clock edge, by adding the momentary bit-period estimate to the last clock edge. The underlying method of functioning can be described algorithmically as follows:    Phase or timing error: e(k)=x0(k)−y(k)    Filtered error: d(k)=F(q−1)·e(k)    Momentary bit-period estimate: Tb(k)=T0+d(k)    Next clock edge: y(k+1)=q·A(q−1)·Tb(k)
Through the targeted selection of coefficients of F(q−1) and A(q−1), the above software PLL can approximate the theoretical PLL transmission function very well, provided it operates offline. In the case of a realization operating in real time, it should be remembered that each of the above processing stages requires a certain processing time. The overall realization-specific delay falsifies the transmission function of the phase-locked loop and can even endanger stability. As a rule of thumb, a realtime-capable software PLL according to the prior art can be used only for the analysis of data streams, of which the bit period is longer than the processing time for the calculation of a new clock edge.